The present invention is generally related to the field of digital analysis and, more particularly, is related to a system and method for adjusting a sampling time in a logic analyzer .
Current manufacturers of high speed computer equipment often need to access data information that is communicated on a data bus or other conductors within the machine for testing or other reasons. Conventional approaches to accessing data on a bus include the use of logic analyzers that provide probes that are placed in electrical contact with the particular conductors in question.
Typically, logical analyzers obtain data transferred on one or more data pathways as well as a clock signal that is synchronized with the data signal(s) on the data pathways that control the sampling function necessary to recover data. Unfortunately, due to the ever increasing speed at which data is transferred across these pathways, it has become more and more difficult to reliably sample the data on the conductors due to the relatively larger effects of skew, part to part variances, and logic analyzer signal loading. To allow for these effects, logic analyzers as well as high speed digital circuits themselves have incorporated means to deskew signals before sampling. Otherwise, the misalignment between the target data signals and the clock signal can result in corrupted data since the data may be sampled when it is transitioning between states rather than in stable regions that represent actual data or other value. In the case of logic analyzers, these means have relied on an operator to adjust the logic analyzer sampling positions using knowledge of the expected data values present on the conductors. This process of adjustment is labor intensive, tedious, and error prone.
In light of the foregoing, the present invention provides a system and method for detecting the stable regions in a data signal to facilitate the alignment between a data signal and a corresponding clock signal. In one embodiment, the system includes a processor coupled to a local interface and a memory coupled to the local interface. The system also includes a boundary detection circuit configured to perform a simultaneous sampling of a reference signal and a delayed version of the reference signal to ascertain a presence or absence of a number of transitions on the reference signal at a selectable position in time with respect to the associated input clock. The reference signal is one of the signals received from the target system and the delayed version of the reference signal is a delayed copy of the reference signal. The present invention also includes boundary detection logic stored on the memory and executed by the processor to control the operation of the boundary detection circuit. The boundary detection logic includes logic to detect a boundary of the stable regions of the reference signal by searching for a boundary between a stable region and an unstable region by sampling a number of positions in the reference signal according to a search pattern.
A method of the present invention comprises the steps of performing a simultaneous sampling of a reference signal and a delayed version of the reference signal to ascertain a number of transitions at a selectable position in time of the reference signal with respect to an associated clock input, and, detecting a boundary of the stable region of the reference signal by sampling a number of the selectable positions of the reference signal according to a search pattern.
An advantage of the invention is that it provides a means for detecting the position of boundaries of a stable region in the reference data signal relative to a clock signal. Once this information is known, then an appropriate delay to apply to the data signal to bring it into alignment with the clock signal or vice versa can be determined. The present invention is also advantageous in that is provides the relative location information in an automated fashion without requiring manual tuning. In addition, the present invention does not require prior knowledge of the sequence of data values tested to achieve the tuning.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.